1. Field of the Invention
The present invention relates to power management in integrated circuits, and more specifically, to clock gating of circuits.
2. Description of the Prior Art
Clock gating is used to reduce power consumption in integrated circuits. Typical clock gating provides a clock signal to functional blocks that are active for one or more clock cycles, and withholds the clock signal when blocks are inactive. When a block is inactive, that is, when its output is not required or is ignored, a clock gate prevents the block from receiving the clock signal. The inactive block does not perform any unnecessary operations, and power is saved.
Generally, neglecting short-circuit power and leakage current, power consumption, PC, in a CMOS circuit C comprising gates g can be expressed as:                               P          C                =                                            1              2                        ·            f            ·                          Vdd                                                                                 ⁢                2                                              ⁢                                    ∑                              g                ∈                C                                      ⁢                          (                                                A                  R                                ·                                  C                  L                  g                                            )                                                          (                  Eqn          ⁢          .1                )            where,                f is clock frequency;        Vdd is the circuit power supply voltage;        Ag is a gate activity factor, and        CLg is gate load capacitance.The aim of clock gating is to reduce circuit activity, A, and by this, reduce the total power consumption, PC according to Eqn.1. Specifically, if sections of the circuit are not required, the activity of these sections should be reduced or eliminated when possible.        
FIG. 1 shows an exemplary prior art clock gate 10 controlling clock signal distribution to a logic circuit 16. The clock gate 10 includes a d-latch 12 and an AND gate 14. The logic circuit 16 outputs an enable signal to the data input of the d-latch 12, which, in conjunction with the AND gate 14, determines if the logic circuit 16 receives the clock signal. When the logic circuit 16 is operational, the enable signal is a logical ‘0’ and the clock gate 10 conveys the clock signal to the logic circuit 16. Similarly, when the logic circuit 16 is not processing data or otherwise not intended to be operational, it outputs a logical ‘1’ to the clock gate 10, which accordingly withholds the clock signal. Providing the enable signal has an adequate source, the implementation of the clock gate 10 can save a significant amount of power in the logic circuit 16 to justify the increased amount of components. While clock gate 10 is well known by those skilled in the art, Long et al. provide an improved design in U.S. Pat. No. 6,232,820, which is incorporated herein by reference.
Conventionally, clock gating has been implemented for major functional blocks of a circuit. Referring to FIG. 2, major functional blocks 20 are supplied a clock signal through clock gates 24. Operations of each functional block 20 are realized by pluralities of registers 22 (data inputs and outputs omitted from FIG. 2 for clarity). The clock gates 24 are provided with an enable signal to activate or deactivate the corresponding functional blocks 20. Typically, buffers 26 are also provided to match clock delays where necessary. During operation, each functional block 20 outputs an enable signal to the corresponding clock gate 24, which accordingly provides or withholds the clock signal. While this functional block level clock gating scheme has advantages, one key disadvantage is coarseness. Specifically, if a single register is required to operate, an entire functional block must be supplied with the clock signal, and thus power may be wasted through unnecessary operations.
Another example of prior art clock gating is illustrated in FIG. 3. A clock signal is selectively provided to individual registers 32 of functional blocks 30 through clock gates 34 and buffers 36. Each register may then be provided with the clock signal as required. A similar structure is disclosed by Minami et al. in U.S. Pat. No. 6,272,667 (FIG. 22), which is incorporated herein by reference. Overall power savings are significantly reduced by power required for the numerous clock gates 34 themselves, however, pinpointing registers that require the clock signal and then precisely providing the clock signal is possible. Implemented at the lowest level of functional block design, clock gating can be performed with fine control al the cost of reduced efficiency.
In the prior art, optimum power savings are not achieved because control of clock distribution is too coarse, being performed at the functional block level and allowing much circuitry to operate unnecessarily; or too fine, being performed at the individual register level wasting power through superfluous clock gates.